/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2020-2022. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * Description:
 * Author: huawei
 * Create: 2020-4-1
 */

#ifndef REG_VPC_MILAN_VPC_REG_H
#define REG_VPC_MILAN_VPC_REG_H

#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <stdint.h>
#endif
#include "vpc_pipe_milan_affine_reg_c_union_define.h"
#include "vpc_pipe_milan_cache_reg_c_union_define.h"
#include "vpc_pipe_milan_histogram_nmanager_reg_c_union_define.h"
#include "vpc_pipe_milan_lut_nmanager_reg_c_union_define.h"
#include "vpc_pipe_milan_pipeTop_reg_c_union_define.h"
#include "vpc_pipe_milan_pixaug_reg_c_union_define.h"
#include "vpc_pipe_milan_pyramid_nmanager_reg_c_union_define.h"
#include "vpc_pipe_milan_resize_reg_c_union_define.h"
#include "vpc_pipe_mosaic_cover_osd_reg_c_union_define.h"
#include "vpc_pipe_milan_rotate_reg_c_union_define.h"
#include "vpc_top_milan_reg_c_union_define.h"
#include "vpc_vlc_milan_reg_c_union_define.h"
#include "vpc_pipe_milan_v1r3_filter_reg_c_union_define.h"

// default value
#define DEFAULT_RD_AXI_LINE_VALUE               0x1FFF0000
#define DEFAULT_RD_AXI_LINE_STRIDE_MASK         0x3FF
#define DEFAULT_RD_IF_CFG_VALUE                 0x80000000
#define DEFAULT_LIMITER_VP_RD_VALUE             0x0F00FFFF

#define DEFAULT_VP_WR_AXI_LINE_VALUE            0x1FFF8000
#define DEFAULT_VP_WR_LINE_STRIDE_MASK          0x3FF
#define DEFAULT_VP_WR_IF_CFG_VALUE              0x80000000
#define DEFAULT_LIMITER_VP_WR_VALUE             0x0F00FFFF

#define HISTOGRAM_READ_SIZE                     0xC00
#define YUVSUM_READ_SIZE                        0x18

// base offset addr
#define VPC_TOP_OFFSET_ADDR                     0x33000
#define VPC_HISTOGRAM_OFFSET_ADDR               0x10000
#define VPC_LUT_OFFSET_ADDR                     0xA000
#define VPC_WARP_OFFSET_ADDR                    0x0B000
#define VPC_CACHE_OFFSET_ADDR                   0x34000
#define VPC_CMDLST_OFFSET_ADDR                  0x32000
#define VPC_FILTER_OFFSET_ADDR                  0x4000
#define VPC_PIXAUG_OFFSET_ADDR                  0xC000
#define VPC_AFFINE_OFFSET_ADDR                  0xD000
#define VPC_ROTATE_OFFSET_ADDR                  0xE000
#define VPC_YUV_SCALER_OFFSET_ADDR              0x3000
#define VPC_PIPELINE_OFFSET_ADDR                0x5000
#define VPC_PIPELINE2_OFFSET_ADDR               0x6000
#define VPC_PIPELINE3_OFFSET_ADDR               0x7000
#define VPC_PYRAMID_OFFSET_ADDR                 0x9000
#define VPC_CVDR_OFFSET_ADDR                    0x10000
#define VPC_BILINEAR0_OFFSET_ADDR               0x0000
#define VPC_BILINEAR2_OFFSET_ADDR               0x1000
#define VPC_CH1_YUVSCALE_OFFSET_ADDR            0x3000 // milan yuv scale offset
#define VPC_REGION_OFFSET_ADDR                  0x18000
#define VPC_NEW_YUVSCALE_OFFSET_ADDR            0x2000 // mini yuv scale offset

// rdma addr for mlv1r3
#define REG_RDMA_LUMA_HEAD_ADDR_L               (VPC_TOP_OFFSET_ADDR + 0xC)
#define REG_RDMA_CHROMA_HEAD_ADDR_L             (VPC_TOP_OFFSET_ADDR + 0x10)
#define REG_RDMA_LUMA_HEAD_STRIDE               (VPC_TOP_OFFSET_ADDR + 0x14)
#define REG_RDMA_LUMA_PAYLOAD_ADDR_L            (VPC_TOP_OFFSET_ADDR + 0x18)
#define REG_RDMA_CHROMA_PAYLOAD_ADDR_L          (VPC_TOP_OFFSET_ADDR + 0x1C)
#define REG_RDMA_LUMA_PAYLOAD_STRIDE            (VPC_TOP_OFFSET_ADDR + 0x20)
#define REG_RDMA_CHROMA_HEAD_STRIDE             (VPC_TOP_OFFSET_ADDR + 0x3C)
#define REG_RDMA_CHROMA_PAYLOAD_STRIDE          (VPC_TOP_OFFSET_ADDR + 0x40)

#define REG_RDMA_LUMA_HEAD_ADDR_H               (VPC_TOP_OFFSET_ADDR + 0xC0)
#define REG_RDMA_CHROMA_HEAD_ADDR_H             (VPC_TOP_OFFSET_ADDR + 0xC4)
#define REG_RDMA_LUMA_PAYLOAD_ADDR_H            (VPC_TOP_OFFSET_ADDR + 0xC8)
#define REG_RDMA_CHROMA_PAYLOAD_ADDR_H          (VPC_TOP_OFFSET_ADDR + 0xCC)

// lut addr
#define VPC_LUT_INPUT0_PIC_SIZE_ADDR            (VPC_LUT_OFFSET_ADDR + 0x004)
#define VPC_LUT_CTRL_ADDR                       (VPC_LUT_OFFSET_ADDR + 0x00C)
#define VPC_LUT_REMAP_Y_OR_R_ADDR               (VPC_LUT_OFFSET_ADDR + 0x400)
#define VPC_LUT_REMAP_U_OR_G_ADDR               (VPC_LUT_OFFSET_ADDR + 0x800)
#define VPC_LUT_REMAP_V_OR_B_ADDR               (VPC_LUT_OFFSET_ADDR + 0xC00)
#define VPC_LUT_GAIN_CTRL_ADDR                  (VPC_LUT_OFFSET_ADDR + 0x010)
#define VPC_LUT_GAIN0_VALUE_ADDR                (VPC_LUT_OFFSET_ADDR + 0x040)
#define VPC_LUT_POSTERIZE_CTRL_ADDR             (VPC_LUT_OFFSET_ADDR + 0x014)
#define VPC_LUT_POSTERIZE0_VALUE_ADDR           (VPC_LUT_OFFSET_ADDR + 0x080)
#define VPC_LUT_THRESHOLD_CTRL_ADDR             (VPC_LUT_OFFSET_ADDR + 0x018)
#define VPC_LUT_THRESHOLD0_VALUE_ADDR           (VPC_LUT_OFFSET_ADDR + 0x0B0)
#define VPC_LUT_CUTOUT_CTRL_ADDR                (VPC_LUT_OFFSET_ADDR + 0x01C)
#define VPC_LUT_CUTOUT0_R_ADDR                  (VPC_LUT_OFFSET_ADDR + 0x0E0)
#define VPC_LUT_CUTOUT0_G_ADDR                  (VPC_LUT_OFFSET_ADDR + 0x0E4)
#define VPC_LUT_CUTOUT0_B_ADDR                  (VPC_LUT_OFFSET_ADDR + 0x0E8)
#define VPC_LUT_WIN0_H                          (VPC_LUT_OFFSET_ADDR + 0x020)
#define VPC_LUT_WIN0_V                          (VPC_LUT_OFFSET_ADDR + 0x024)
// resize addr
#define VPC_RESIZE_ILEFT_ADDR                   (VPC_BILINEAR0_OFFSET_ADDR + 0x010)
#define VPC_RESIZE_IRIGHT_ADDR                  (VPC_BILINEAR0_OFFSET_ADDR + 0x014)
#define VPC_RESIZE_ITOP_ADDR                    (VPC_BILINEAR0_OFFSET_ADDR + 0x018)
#define VPC_RESIZE_IBOTTOM_ADDR                 (VPC_BILINEAR0_OFFSET_ADDR + 0x01C)
#define VPC_RESIZE_OLEFT_ADDR                   (VPC_BILINEAR0_OFFSET_ADDR + 0x020)
#define VPC_RESIZE_ORIGHT_ADDR                  (VPC_BILINEAR0_OFFSET_ADDR + 0x024)
#define VPC_RESIZE_OTOP_ADDR                    (VPC_BILINEAR0_OFFSET_ADDR + 0x028)
#define VPC_RESIZE_OBOTTOM_ADDR                 (VPC_BILINEAR0_OFFSET_ADDR + 0x02C)
#define REG_VPC_RESIZE_IN_WIDTH                 (VPC_BILINEAR0_OFFSET_ADDR + 0x000)
#define REG_VPC_RESIZE_IN_HEIGHT                (VPC_BILINEAR0_OFFSET_ADDR + 0x004)
#define REG_VPC_RESIZE_OUT_WIDTH                (VPC_BILINEAR0_OFFSET_ADDR + 0x008)
#define REG_VPC_RESIZE_OUT_HEIGHT               (VPC_BILINEAR0_OFFSET_ADDR + 0x00C)
#define REG_VPC_RESIZE_MISC_CTRL                (VPC_BILINEAR0_OFFSET_ADDR + 0x100)
#define REG_VPC_RESIZE_RND_CTRL0                (VPC_BILINEAR0_OFFSET_ADDR + 0x110)

#define VPC_RESIZE2_ILEFT_ADDR                  (VPC_BILINEAR2_OFFSET_ADDR + 0x010)
#define VPC_RESIZE2_IRIGHT_ADDR                 (VPC_BILINEAR2_OFFSET_ADDR + 0x014)
#define VPC_RESIZE2_ITOP_ADDR                   (VPC_BILINEAR2_OFFSET_ADDR + 0x018)
#define VPC_RESIZE2_IBOTTOM_ADDR                (VPC_BILINEAR2_OFFSET_ADDR + 0x01C)
#define VPC_RESIZE2_OLEFT_ADDR                  (VPC_BILINEAR2_OFFSET_ADDR + 0x020)
#define VPC_RESIZE2_ORIGHT_ADDR                 (VPC_BILINEAR2_OFFSET_ADDR + 0x024)
#define VPC_RESIZE2_OTOP_ADDR                   (VPC_BILINEAR2_OFFSET_ADDR + 0x028)
#define VPC_RESIZE2_OBOTTOM_ADDR                (VPC_BILINEAR2_OFFSET_ADDR + 0x02C)
#define REG_VPC_RESIZE2_IN_WIDTH                (VPC_BILINEAR2_OFFSET_ADDR + 0x000)
#define REG_VPC_RESIZE2_IN_HEIGHT               (VPC_BILINEAR2_OFFSET_ADDR + 0x004)
#define REG_VPC_RESIZE2_OUT_WIDTH               (VPC_BILINEAR2_OFFSET_ADDR + 0x008)
#define REG_VPC_RESIZE2_OUT_HEIGHT              (VPC_BILINEAR2_OFFSET_ADDR + 0x00C)
#define REG_VPC_RESIZE2_MISC_CTRL               (VPC_BILINEAR2_OFFSET_ADDR + 0x100)
#define REG_VPC_RESIZE2_RND_CTRL0               (VPC_BILINEAR2_OFFSET_ADDR + 0x110)

// blend addr
#define REG_VPC_PYRAMID_BLENDING_MODE           (VPC_PYRAMID_OFFSET_ADDR + 0x0cc)
#define REG_VPC_PYRAMID_LAY0_IN_SIZE            (VPC_PYRAMID_OFFSET_ADDR + 0x0d0)
#define REG_VPC_PYRAMID_LAY1_IN_SIZE            (VPC_PYRAMID_OFFSET_ADDR + 0x0d4)
#define REG_VPC_PYRAMID_LEFT_POSITION           (VPC_PYRAMID_OFFSET_ADDR + 0x0d8)
#define REG_VPC_PYRAMID_COEF_ALPHA              (VPC_PYRAMID_OFFSET_ADDR + 0x0e0)
#define REG_VPC_PYRAMID_COEF_BETA               (VPC_PYRAMID_OFFSET_ADDR + 0x0e4)
#define REG_VPC_PYRAMID_COEF_GAMMA              (VPC_PYRAMID_OFFSET_ADDR + 0x0e8)

// cvdr addr
#define REG_VPC_CVDR_VP_RD_CFG_0                (VPC_CVDR_OFFSET_ADDR + 0x0A30)
#define REG_VPC_CVDR_VP_RD_CFG_1                (VPC_CVDR_OFFSET_ADDR + 0x0A50)
#define REG_VPC_CVDR_VP_RD_CFG_2                (VPC_CVDR_OFFSET_ADDR + 0x0A70)
#define REG_VPC_CVDR_VP_RD_AXI_LINE_0           (VPC_CVDR_OFFSET_ADDR + 0x0A40)
#define REG_VPC_CVDR_LIMITER_VP_RD_0            (VPC_CVDR_OFFSET_ADDR + 0x1230)
#define REG_VPC_CVDR_LIMITER_VP_RD_1            (VPC_CVDR_OFFSET_ADDR + 0x1234)
#define REG_VPC_CVDR_VP_RD_AXI_LINE_1           (VPC_CVDR_OFFSET_ADDR + 0x0A60)
#define REG_VPC_CVDR_LIMITER_VP_WR_0            (VPC_CVDR_OFFSET_ADDR + 0x0830)
#define REG_VPC_CVDR_LIMITER_VP_WR_1            (VPC_CVDR_OFFSET_ADDR + 0x0834)
#define REG_VPC_CVDR_VP_WR_CFG_0                (VPC_CVDR_OFFSET_ADDR + 0x0030)
#define REG_VPC_CVDR_VP_WR_CFG_1                (VPC_CVDR_OFFSET_ADDR + 0x0040)
#define REG_VPC_CVDR_VP_RD_AXI_FS_0             (VPC_CVDR_OFFSET_ADDR + 0x0A3C)
#define REG_VPC_CVDR_VP_RD_AXI_FS_1             (VPC_CVDR_OFFSET_ADDR + 0x0A5C)

// tod addr
#define REG_VPC_TOP_CONTROL_1                   (VPC_TOP_OFFSET_ADDR + 0x000)
#define REG_VPC_TOP_CONTROL_2                   (VPC_TOP_OFFSET_ADDR + 0x004)
#define REG_VPC_TOP_CONTROL_3                   (VPC_TOP_OFFSET_ADDR + 0x008)
#define REG_VPC_INPUT0_PIC_SIZE                 (VPC_TOP_OFFSET_ADDR + 0x024)
#define REG_VPC_INPUT1_PIC_SIZE                 (VPC_TOP_OFFSET_ADDR + 0x028)
#define REG_VPC_OUTPUT_PIC_SIZE                 (VPC_TOP_OFFSET_ADDR + 0x02C)
#define REG_VPC_OUTPUT_FORMAT                   (VPC_TOP_OFFSET_ADDR + 0x030)
#define REG_VPC_OUTPUT2_PIC_SIZE                (VPC_TOP_OFFSET_ADDR + 0x034)
#define REG_VPC_OUTPUT3_PIC_SIZE                (VPC_TOP_OFFSET_ADDR + 0x038)
#define REG_VPC_TOP_RDMA_HADDR1_H               (VPC_TOP_OFFSET_ADDR + 0x0C0)
#define REG_VPC_NORM_CVDR_INT_MASK4             (VPC_TOP_OFFSET_ADDR + 0x11C)
#define REG_VPC_NORM_CVDR_INT_CLR1              (VPC_TOP_OFFSET_ADDR + 0x130)
#define REG_VPC_NORM_CVDR_INT_CLR2              (VPC_TOP_OFFSET_ADDR + 0x134)
#define REG_VPC_NORM_CVDR_INT_CLR3              (VPC_TOP_OFFSET_ADDR + 0x138)
#define REG_VPC_NORM_CVDR_INT_CLR4              (VPC_TOP_OFFSET_ADDR + 0x13C)
#define REG_VPC_NORM_INT_CLR2                   (VPC_TOP_OFFSET_ADDR + 0x15C)
#define REG_VPC_ERR_INT_CLR                     (VPC_TOP_OFFSET_ADDR + 0x170)
#define REG_VPC_ERR_OUT_DMUXEN                  (VPC_TOP_OFFSET_ADDR + 0x17C)
#define REG_VPC_EOF_INT1_MERGE_ENABLE_PIPE      (VPC_TOP_OFFSET_ADDR + 0x180)
#define REG_VPC_EOF_INT1_MERGE_ENABLE_RDMA_CVDR (VPC_TOP_OFFSET_ADDR + 0x184)
#define REG_VPC_CMDLIST_IN_INT_CTRL             (VPC_TOP_OFFSET_ADDR + 0x194)
#define REG_VPC_NORM_INT_MASK2                  (VPC_TOP_OFFSET_ADDR + 0x154)
#define REG_VPC_ERR_INT_MASK                    (VPC_TOP_OFFSET_ADDR + 0x168)
#define REG_VPC_BUS_CTRL_4                      (VPC_TOP_OFFSET_ADDR + 0x07C)
#define REG_VPC_BUS_CTRL_7                      (VPC_TOP_OFFSET_ADDR + 0x088)

// yuv scaler addr
#define REG_YUV_SCALER_IHLEFT                   (VPC_YUV_SCALER_OFFSET_ADDR + 0x00)
#define REG_YUV_SCALER_IHRIGHT                  (VPC_YUV_SCALER_OFFSET_ADDR + 0x04)
#define REG_YUV_SCALER_IVTOP                    (VPC_YUV_SCALER_OFFSET_ADDR + 0x0C)
#define REG_YUV_SCALER_IVBOTTOM                 (VPC_YUV_SCALER_OFFSET_ADDR + 0x10)
#define REG_YUV_SCALER_IHINC                    (VPC_YUV_SCALER_OFFSET_ADDR + 0x18)
#define REG_YUV_SCALER_IVINC                    (VPC_YUV_SCALER_OFFSET_ADDR + 0x1C)
#define REG_YUV_SCALER_BYPASS                   (VPC_YUV_SCALER_OFFSET_ADDR + 0x24)
#define REG_YUV_SCALER_IWIDTH                   (VPC_YUV_SCALER_OFFSET_ADDR + 0x30)
#define REG_YUV_SCALER_IHEIGHT                  (VPC_YUV_SCALER_OFFSET_ADDR + 0x34)
#define REG_YUV_SCALER_OWIDTH                   (VPC_YUV_SCALER_OFFSET_ADDR + 0x38)
#define REG_YUV_SCALER_OHEIGHT                  (VPC_YUV_SCALER_OFFSET_ADDR + 0x3C)
#define REG_YUV_SCALER_COEFF_H_Y0               (VPC_YUV_SCALER_OFFSET_ADDR + 0x060)
#define REG_YUV_SCALER_COEFF_H_Y1               (VPC_YUV_SCALER_OFFSET_ADDR + 0x080)
#define REG_YUV_SCALER_COEFF_V_Y0               (VPC_YUV_SCALER_OFFSET_ADDR + 0x0A0)
#define REG_YUV_SCALER_COEFF_V_Y1               (VPC_YUV_SCALER_OFFSET_ADDR + 0x0C0)
#define REG_YUV_SCALER_COEFF_H_UV0              (VPC_YUV_SCALER_OFFSET_ADDR + 0x0E0)
#define REG_YUV_SCALER_COEFF_H_UV1              (VPC_YUV_SCALER_OFFSET_ADDR + 0x100)
#define REG_YUV_SCALER_COEFF_V_UV0              (VPC_YUV_SCALER_OFFSET_ADDR + 0x120)
#define REG_YUV_SCALER_COEFF_V_UV1              (VPC_YUV_SCALER_OFFSET_ADDR + 0x140)
// yuv scaler addr on mini v2
#define REG_NEW_SCALER_IHLEFT_INT               (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x00)
#define REG_NEW_SCALER_IHLEFT_DEC               (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x04)
#define REG_NEW_SCALER_IVTOP_INT                (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x0C)
#define REG_NEW_SCALER_IVBOTTOM_INT             (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x10)

#define REG_NEW_SCALER_IHINC                    (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x28)
#define REG_NEW_SCALER_IVINC                    (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x2C)
#define REG_NEW_SCALER_BYPASS                   (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x30)

#define REG_NEW_SCALER_FORMAT                   (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x34)

#define REG_NEW_SCALER_IWIDTH                   (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x40)
#define REG_NEW_SCALER_IHEIGHT                  (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x44)
#define REG_NEW_SCALER_OWIDTH                   (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x48)
#define REG_NEW_SCALER_OHEIGHT                  (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x4C)

#define REG_NEW_SCALER_COEFF_H_Y0               (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x200)
#define REG_NEW_SCALER_COEFF_H_Y1               (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x204)
#define REG_NEW_SCALER_COEFF_H_Y2               (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x208)

#define REG_NEW_SCALER_COEFF_H_UV0              (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x600)
#define REG_NEW_SCALER_COEFF_H_UV1              (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x604)

#define REG_NEW_SCALER_COEFF_V_Y0               (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x400)
#define REG_NEW_SCALER_COEFF_V_Y1               (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x404)

#define REG_NEW_SCALER_COEFF_V_UV0              (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x800)
#define REG_NEW_SCALER_COEFF_V_UV1              (VPC_NEW_YUVSCALE_OFFSET_ADDR + 0x804)

// pipeline addr
#define REG_VPC_PIPELINE_IN_SWAP                (VPC_PIPELINE_OFFSET_ADDR + 0x000)
#define REG_VPC_PIPELINE_UVUP_FILTER            (VPC_PIPELINE_OFFSET_ADDR + 0x004)
#define REG_VPC_PIPELINE_PIPE_CTRL              (VPC_PIPELINE_OFFSET_ADDR + 0x008)
#define REG_VPC_PIPELINE_XFLIP_LUT_HISTOGRAM    (VPC_PIPELINE_OFFSET_ADDR + 0x00C)
#define REG_VPC_PIPELINE_OUT_SWAP               (VPC_PIPELINE_OFFSET_ADDR + 0x018)
#define REG_VPC_PIPELINE_UVDEC_1                (VPC_PIPELINE_OFFSET_ADDR + 0x01C)
#define XFLIP_CHANNEL_1_WIDTH_HEIGHT_REG        (VPC_PIPELINE_OFFSET_ADDR + 0x020)
#define REG_VPC_PIPELINE_PRECROP_1              (VPC_PIPELINE_OFFSET_ADDR + 0x028)
#define REG_VPC_PIPELINE_POSTCROP1_1            (VPC_PIPELINE_OFFSET_ADDR + 0x030)
#define REG_VPC_PIPELINE_POSTCROP1_2            (VPC_PIPELINE_OFFSET_ADDR + 0x034)
#define REG_VPC_PIPELINE_POSTCROP2_1            (VPC_PIPELINE_OFFSET_ADDR + 0x1030)
#define REG_VPC_PIPELINE_POSTCROP2_2            (VPC_PIPELINE_OFFSET_ADDR + 0x1034)
#define REG_VPC_CSC_ALPHA_PADDING               (VPC_PIPELINE_OFFSET_ADDR + 0x100)
#define REG_VPC_IN0_444_TO_422_FILTER           (VPC_PIPELINE_OFFSET_ADDR + 0x060)
#define REG_VPC_OUT_444_TO_422_FILTER           (VPC_PIPELINE_OFFSET_ADDR + 0x080)
#define REG_VPC_OUT_422_TO_420_FILTER           (VPC_PIPELINE_OFFSET_ADDR + 0x08C)
#define REG_VPC_PRE_PADDING_MODE                (VPC_PIPELINE_OFFSET_ADDR + 0x090)
#define REG_VPC_PRE_PADDING_SIZE_0              (VPC_PIPELINE_OFFSET_ADDR + 0x094)
#define REG_VPC_PRE_PADDING_SIZE_1              (VPC_PIPELINE_OFFSET_ADDR + 0x098)
#define REG_VPC_PRE_PADDING_VALUE_HOR_L         (VPC_PIPELINE_OFFSET_ADDR + 0x09c)
#define REG_VPC_PRE_PADDING_VALUE_HOR_M         (VPC_PIPELINE_OFFSET_ADDR + 0x0a0)
#define REG_VPC_PRE_PADDING_VALUE_HOR_H         (VPC_PIPELINE_OFFSET_ADDR + 0x0a4)
#define REG_VPC_PRE_PADDING_VALUE_VER_L         (VPC_PIPELINE_OFFSET_ADDR + 0x0a8)
#define REG_VPC_PRE_PADDING_VALUE_VER_M         (VPC_PIPELINE_OFFSET_ADDR + 0x0ac)
#define REG_VPC_PRE_PADDING_VALUE_VER_H         (VPC_PIPELINE_OFFSET_ADDR + 0x0b0)
#define REG_VPC_PRE_PADDING_RESOLUTION          (VPC_PIPELINE_OFFSET_ADDR + 0x0B4)
#define REG_VPC_POST_PADDING_MODE               (VPC_PIPELINE_OFFSET_ADDR + 0x0c0)
#define REG_VPC_POST_PADDING_SIZE_0             (VPC_PIPELINE_OFFSET_ADDR + 0x0c4)
#define REG_VPC_POST_PADDING_SIZE_1             (VPC_PIPELINE_OFFSET_ADDR + 0x0c8)
#define REG_VPC_POST_PADDING_VALUE_HOR_L        (VPC_PIPELINE_OFFSET_ADDR + 0x0cc)
#define REG_VPC_POST_PADDING_VALUE_HOR_M        (VPC_PIPELINE_OFFSET_ADDR + 0x0d0)
#define REG_VPC_POST_PADDING_VALUE_HOR_H        (VPC_PIPELINE_OFFSET_ADDR + 0x0d4)
#define REG_VPC_POST_PADDING_VALUE_VER_L        (VPC_PIPELINE_OFFSET_ADDR + 0x0d8)
#define REG_VPC_POST_PADDING_VALUE_VER_M        (VPC_PIPELINE_OFFSET_ADDR + 0x0dc)
#define REG_VPC_POST_PADDING_VALUE_VER_H        (VPC_PIPELINE_OFFSET_ADDR + 0x0e0)
#define REG_VPC_POST_PADDING_RESOLUTION         (VPC_PIPELINE_OFFSET_ADDR + 0x0e4)
#define REG_VPC_POST_PADDING2_MODE              (VPC_PIPELINE_OFFSET_ADDR + 0x10c0)
#define REG_VPC_POST_PADDING2_SIZE_0            (VPC_PIPELINE_OFFSET_ADDR + 0x10c4)
#define REG_VPC_POST_PADDING2_SIZE_1            (VPC_PIPELINE_OFFSET_ADDR + 0x10c8)
#define REG_VPC_POST_PADDING2_VALUE_HOR_L       (VPC_PIPELINE_OFFSET_ADDR + 0x10cc)
#define REG_VPC_POST_PADDING2_VALUE_HOR_M       (VPC_PIPELINE_OFFSET_ADDR + 0x10d0)
#define REG_VPC_POST_PADDING2_VALUE_HOR_H       (VPC_PIPELINE_OFFSET_ADDR + 0x10d4)
#define REG_VPC_POST_PADDING2_VALUE_VER_L       (VPC_PIPELINE_OFFSET_ADDR + 0x10d8)
#define REG_VPC_POST_PADDING2_VALUE_VER_M       (VPC_PIPELINE_OFFSET_ADDR + 0x10dc)
#define REG_VPC_POST_PADDING2_VALUE_VER_H       (VPC_PIPELINE_OFFSET_ADDR + 0x10e0)
#define REG_VPC_POST_PADDING2_RESOLUTION        (VPC_PIPELINE_OFFSET_ADDR + 0x10e4)
#define REG_VPC_CSC_ENABLE                      (VPC_PIPELINE_OFFSET_ADDR + 0x014)
#define REG_VPC_IN0_CSC_0                       (VPC_PIPELINE_OFFSET_ADDR + 0x110)
#define REG_VPC_OUT_CSC_0                       (VPC_PIPELINE_OFFSET_ADDR + 0x310)
#define REG_VPC_IN0CSC_MODE                     (VPC_PIPELINE_OFFSET_ADDR + 0x104)
#define REG_VPC_OUTCSC_MODE                     (VPC_PIPELINE_OFFSET_ADDR + 0x300)
#define REG_VPC_POINTNET_ID                     (VPC_PIPELINE_OFFSET_ADDR + 0x404)
#define REG_VPC_POINTNET_M                      (VPC_PIPELINE_OFFSET_ADDR + 0x408)
#define REG_VPC_POINTNET_N                      (VPC_PIPELINE_OFFSET_ADDR + 0x40C)
#define REG_VPC_POINTNET_X_OFFSET               (VPC_PIPELINE_OFFSET_ADDR + 0x410)
#define REG_VPC_POINTNET_TR                     (VPC_PIPELINE_OFFSET_ADDR + 0x418)

#define REG_VPC_CVT_CTRL                        (VPC_PIPELINE_OFFSET_ADDR + 0x480)
#define REG_VPC_CVT_SCALE                       (VPC_PIPELINE_OFFSET_ADDR + 0x484)

#define REG_LINE_BLK_CONVERT                    (VPC_PIPELINE_OFFSET_ADDR + 0x4A0)
#define REG_LINE_BLK_CONVERT_INPUT_SIZE         (VPC_PIPELINE_OFFSET_ADDR + 0x4A4)
#define REG_BLK_CONVERT_BLK_SIZE                (VPC_PIPELINE_OFFSET_ADDR + 0x4A8)

#define REG_PIPELINE_HSV_MODE_SET               (VPC_PIPELINE_OFFSET_ADDR + 0x0440)
#define REG_PIPELINE_HSV_SCALE_SAT              (VPC_PIPELINE_OFFSET_ADDR + 0x0444)
#define REG_PIPELINE_HSV_DELTA_HUE              (VPC_PIPELINE_OFFSET_ADDR + 0x0448)

#define REG_PIPELINE_OUTCSS_NORMALIZE_IN        (VPC_PIPELINE_OFFSET_ADDR + 0x0388)
#define REG_PIPELINE_OUTCSS_NORMALIZE_OUT       (VPC_PIPELINE_OFFSET_ADDR + 0x038c)
#define REG_PIPELINE_OUTCSS_CVT_MODE            (VPC_PIPELINE_OFFSET_ADDR + 0x0390)

#define REG_VPC_PIPELINE2_UVUP_FILTER           (VPC_PIPELINE2_OFFSET_ADDR + 0x004)
#define REG_VPC_OUT2_CSC_ENABLE                 (VPC_PIPELINE2_OFFSET_ADDR + 0x014)
#define REG_VPC_PIPELINE2_OUT_SWAP              (VPC_PIPELINE2_OFFSET_ADDR + 0x018)
#define REG_VPC_OUT2_444_TO_422_FILTER          (VPC_PIPELINE2_OFFSET_ADDR + 0x080)
#define REG_VPC_OUT2_422_TO_420_FILTER          (VPC_PIPELINE2_OFFSET_ADDR + 0x08C)
#define REG_VPC_OUT2_CSC_ALPHA_PADDING          (VPC_PIPELINE2_OFFSET_ADDR + 0x100)
#define REG_VPC_OUT2_CSC_MODE                   (VPC_PIPELINE2_OFFSET_ADDR + 0x300)
#define REG_VPC_OUT2_CSC_0                      (VPC_PIPELINE2_OFFSET_ADDR + 0x310)
#define REG_VPC_PIPELINE3_UVUP_FILTER           (VPC_PIPELINE3_OFFSET_ADDR + 0x004)
#define REG_VPC_OUT3_CSC_ENABLE                 (VPC_PIPELINE3_OFFSET_ADDR + 0x014)
#define REG_VPC_PIPELINE3_OUT_SWAP              (VPC_PIPELINE3_OFFSET_ADDR + 0x018)
#define REG_VPC_OUT3_444_TO_422_FILTER          (VPC_PIPELINE3_OFFSET_ADDR + 0x080)
#define REG_VPC_OUT3_422_TO_420_FILTER          (VPC_PIPELINE3_OFFSET_ADDR + 0x08C)
#define REG_VPC_OUT3_CSC_ALPHA_PADDING          (VPC_PIPELINE3_OFFSET_ADDR + 0x100)
#define REG_VPC_OUT3_CSC_MODE                   (VPC_PIPELINE3_OFFSET_ADDR + 0x300)
#define REG_VPC_OUT3_CSC_0                      (VPC_PIPELINE3_OFFSET_ADDR + 0x310)

// pixaug addr
#define REG_PIXAUG_NORMALIZE_EN                 (VPC_PIXAUG_OFFSET_ADDR + 0x0330)
#define REG_PIXAUG_NORMALIZE_MODE               (VPC_PIXAUG_OFFSET_ADDR + 0x0334)
#define REG_PIXAUG_NORMALIZE_SCALE_R            (VPC_PIXAUG_OFFSET_ADDR + 0x0338)
#define REG_PIXAUG_NORMALIZE_SCALE_G            (VPC_PIXAUG_OFFSET_ADDR + 0x033C)
#define REG_PIXAUG_NORMALIZE_SCALE_B            (VPC_PIXAUG_OFFSET_ADDR + 0x0340)
#define REG_PIXAUG_NORMALIZE_DELTA_R            (VPC_PIXAUG_OFFSET_ADDR + 0x0344)
#define REG_PIXAUG_NORMALIZE_DELTA_G            (VPC_PIXAUG_OFFSET_ADDR + 0x0348)
#define REG_PIXAUG_NORMALIZE_DELTA_B            (VPC_PIXAUG_OFFSET_ADDR + 0x034C)
#define REG_PIXAUG_ENHANCE_EN                   (VPC_PIXAUG_OFFSET_ADDR + 0x0004)
#define REG_PIXAUG_ENHANCE_ADDER                (VPC_PIXAUG_OFFSET_ADDR + 0x0200)
#define REG_PIXAUG_ENHANCE_MULTIPLE             (VPC_PIXAUG_OFFSET_ADDR + 0x0204)
#define REG_PIXAUG_CONTRAST_EN                  (VPC_PIXAUG_OFFSET_ADDR + 0x000C)
#define REG_PIXAUG_CONTRAST_FACTOR              (VPC_PIXAUG_OFFSET_ADDR + 0x0208)
#define REG_PIXAUG_CONTRAST_MEAN_R              (VPC_PIXAUG_OFFSET_ADDR + 0x020C)
#define REG_PIXAUG_CONTRAST_MEAN_G              (VPC_PIXAUG_OFFSET_ADDR + 0x0210)
#define REG_PIXAUG_CONTRAST_MEAN_B              (VPC_PIXAUG_OFFSET_ADDR + 0x0214)
#define REG_PIXAUG_CLIP_EN                      (VPC_PIXAUG_OFFSET_ADDR + 0x0350)
#define REG_PIXAUG_MAX_VALUE_R                  (VPC_PIXAUG_OFFSET_ADDR + 0x0354)
#define REG_PIXAUG_MIN_VALUE_R                  (VPC_PIXAUG_OFFSET_ADDR + 0x0358)
#define REG_PIXAUG_MAX_VALUE_G                  (VPC_PIXAUG_OFFSET_ADDR + 0x035C)
#define REG_PIXAUG_MIN_VALUE_G                  (VPC_PIXAUG_OFFSET_ADDR + 0x0360)
#define REG_PIXAUG_MAX_VALUE_B                  (VPC_PIXAUG_OFFSET_ADDR + 0x0364)
#define REG_PIXAUG_MIN_VALUE_B                  (VPC_PIXAUG_OFFSET_ADDR + 0x0368)
#define REG_PIXAUG_CVAL_R                       (VPC_PIXAUG_OFFSET_ADDR + 0x036C)
#define REG_PIXAUG_CVAL_G                       (VPC_PIXAUG_OFFSET_ADDR + 0x0370)
#define REG_PIXAUG_CVAL_B                       (VPC_PIXAUG_OFFSET_ADDR + 0x0374)

// filter addr
#define REG_FILTER_CONTROL0                     (VPC_FILTER_OFFSET_ADDR + 0x0000)
#define REG_FILTER_CONTROL1                     (VPC_FILTER_OFFSET_ADDR + 0x0004)
#define REG_FILTER_INSIZE                       (VPC_FILTER_OFFSET_ADDR + 0x0008)
#define REG_FILTER_OUTSIZE                      (VPC_FILTER_OFFSET_ADDR + 0x000C)
#define REG_FILTER_PADDING_MODE                 (VPC_FILTER_OFFSET_ADDR + 0x0010)
#define REG_FILTER_H_PADDING_VALUE1             (VPC_FILTER_OFFSET_ADDR + 0x0014)
#define REG_FILTER_H_PADDING_VALUE2             (VPC_FILTER_OFFSET_ADDR + 0x0018)
#define REG_FILTER_H_PADDING_VALUE3             (VPC_FILTER_OFFSET_ADDR + 0x001C)
#define REG_FILTER_V_PADDING_VALUE1             (VPC_FILTER_OFFSET_ADDR + 0x0020)
#define REG_FILTER_V_PADDING_VALUE2             (VPC_FILTER_OFFSET_ADDR + 0x0024)
#define REG_FILTER_V_PADDING_VALUE3             (VPC_FILTER_OFFSET_ADDR + 0x0028)
#define REG_FILTER_COEFF1                       (VPC_FILTER_OFFSET_ADDR + 0x0044)
#define REG_FILTER_COEFF2                       (VPC_FILTER_OFFSET_ADDR + 0x0048)
#define REG_FILTER_COEFF3                       (VPC_FILTER_OFFSET_ADDR + 0x004C)
#define REG_FILTER_COEFF4                       (VPC_FILTER_OFFSET_ADDR + 0x0050)
#define REG_FILTER_COEFF5                       (VPC_FILTER_OFFSET_ADDR + 0x0054)
#define REG_FILTER_COEFF6                       (VPC_FILTER_OFFSET_ADDR + 0x0058)
#define REG_FILTER_COEFF7                       (VPC_FILTER_OFFSET_ADDR + 0x005C)
#define REG_FILTER_COEFF8                       (VPC_FILTER_OFFSET_ADDR + 0x0060)
#define REG_FILTER_COEFF9                       (VPC_FILTER_OFFSET_ADDR + 0x0064)
#define REG_FILTER_COEFF10                      (VPC_FILTER_OFFSET_ADDR + 0x0068)
#define REG_FILTER_COEFF11                      (VPC_FILTER_OFFSET_ADDR + 0x006C)
#define REG_FILTER_COEFF12                      (VPC_FILTER_OFFSET_ADDR + 0x0070)
#define REG_FILTER_COEFF13                      (VPC_FILTER_OFFSET_ADDR + 0x0074)
#define REG_FILTER_COEFF14                      (VPC_FILTER_OFFSET_ADDR + 0x0078)
#define REG_FILTER_COEFF15                      (VPC_FILTER_OFFSET_ADDR + 0x007C)
#define REG_FILTER_COEFF16                      (VPC_FILTER_OFFSET_ADDR + 0x0080)
#define REG_FILTER_COEFF17                      (VPC_FILTER_OFFSET_ADDR + 0x0084)
#define REG_FILTER_COEFF18                      (VPC_FILTER_OFFSET_ADDR + 0x0088)
#define REG_FILTER_COEFF19                      (VPC_FILTER_OFFSET_ADDR + 0x008C)
#define REG_FILTER_COEFF20                      (VPC_FILTER_OFFSET_ADDR + 0x0090)
#define REG_FILTER_COEFF21                      (VPC_FILTER_OFFSET_ADDR + 0x0094)
#define REG_FILTER_COEFF22                      (VPC_FILTER_OFFSET_ADDR + 0x0098)
#define REG_FILTER_COEFF23                      (VPC_FILTER_OFFSET_ADDR + 0x009C)
#define REG_FILTER_COEFF24                      (VPC_FILTER_OFFSET_ADDR + 0x00A0)
#define REG_FILTER_COEFF25                      (VPC_FILTER_OFFSET_ADDR + 0x00A4)
#define REG_FILTER_SCALE                        (VPC_FILTER_OFFSET_ADDR + 0x00A8)
#define REG_FILTER_DELTA                        (VPC_FILTER_OFFSET_ADDR + 0x00AC)
#define REG_FILTER_BLUR_CONTROL                 (VPC_FILTER_OFFSET_ADDR + 0x0040)
#define REG_FILTER_SORT_CONTROL                 (VPC_FILTER_OFFSET_ADDR + 0x00C0)
#define REG_FILTER_RND_MODE                     (VPC_FILTER_OFFSET_ADDR + 0x002C)
#define REG_FILTER_START_POS                    (VPC_FILTER_OFFSET_ADDR + 0x0034)
#define REG_FILTER_END_POS                      (VPC_FILTER_OFFSET_ADDR + 0x0038)
#define REG_FILTER_BLUR_CTRL                    (VPC_FILTER_OFFSET_ADDR + 0x0040)

// histogram addr
#define REG_HISTOGRAM_MODE                      (VPC_HISTOGRAM_OFFSET_ADDR + 0x0D00)
#define REG_HISTOGRAM_CLEAR_MODE                (VPC_HISTOGRAM_OFFSET_ADDR + 0x0D04)
#define REG_HISTOGRAM_READ_ADDR                 (VPC_HISTOGRAM_OFFSET_ADDR + 0x0000)
#define REG_YUVSUM_READ_ADDR                    (VPC_HISTOGRAM_OFFSET_ADDR + 0x0D10)

// cache addr
#define REG_CACHE_MODE                          (VPC_CACHE_OFFSET_ADDR + 0x0)
#define REG_CACHE_CHANNEL0_IMAGE0_BADDR_L       (VPC_CACHE_OFFSET_ADDR + 0x8)
#define REG_CACHE_CHANNEL0_IMAGE0_BADDR_H       (VPC_CACHE_OFFSET_ADDR + 0xc)
#define REG_CACHE_CHANNEL0_IMAGE0_STRIDE        (VPC_CACHE_OFFSET_ADDR + 0x88)
#define REG_CACHE_CHANNEL0_IMAGE1_BADDR_L       (VPC_CACHE_OFFSET_ADDR + 0x10)
#define REG_CACHE_CHANNEL0_IMAGE1_BADDR_H       (VPC_CACHE_OFFSET_ADDR + 0x14)
#define REG_CACHE_CHANNEL0_IMAGE1_STRIDE        (VPC_CACHE_OFFSET_ADDR + 0x8C)
#define REG_CACHE_CHANNEL0_IMAGE2_BADDR_L       (VPC_CACHE_OFFSET_ADDR + 0x18)
#define REG_CACHE_CHANNEL0_IMAGE2_BADDR_H       (VPC_CACHE_OFFSET_ADDR + 0x1c)
#define REG_CACHE_CHANNEL0_IMAGE2_STRIDE        (VPC_CACHE_OFFSET_ADDR + 0x90)
#define REG_CACHE_PICTURE_SIZE_3D               (VPC_CACHE_OFFSET_ADDR + 0x20)
// affine addr
#define REG_AFFINE_OUT_SIZE                     (VPC_AFFINE_OFFSET_ADDR + 0x00)
#define REG_AFFINE_SRC_SIZE                     (VPC_AFFINE_OFFSET_ADDR + 0x04)
#define REG_AFFINE_LUT_BASE_ADDR_H              (VPC_AFFINE_OFFSET_ADDR + 0x08)
#define REG_AFFINE_LUT_BASE_ADDR_L              (VPC_AFFINE_OFFSET_ADDR + 0x0C)
#define REG_AFFINE_LUT_STRIDE                   (VPC_AFFINE_OFFSET_ADDR + 0x10)
#define REG_AFFINE_OUT_BASE_ADDR_H              (VPC_AFFINE_OFFSET_ADDR + 0x14)
#define REG_AFFINE_OUT_BASE_ADDR_L              (VPC_AFFINE_OFFSET_ADDR + 0x18)
#define REG_AFFINE_OUT_STRIDE                   (VPC_AFFINE_OFFSET_ADDR + 0x1C)
#define REG_AFFINE_BLK_SIZE                     (VPC_AFFINE_OFFSET_ADDR + 0x20)
#define REG_AFFINE_MODE                         (VPC_AFFINE_OFFSET_ADDR + 0x28)
#define REG_AFFINE_INVALID_PIX_H                (VPC_AFFINE_OFFSET_ADDR + 0x44)
#define REG_AFFINE_INVALID_PIX_M                (VPC_AFFINE_OFFSET_ADDR + 0x48)
#define REG_AFFINE_INVALID_PIX_L                (VPC_AFFINE_OFFSET_ADDR + 0x4C)
#define REG_AFFINE_MATRIX_0                     (VPC_AFFINE_OFFSET_ADDR + 0x2C)
#define REG_AFFINE_MATRIX_6                     (VPC_AFFINE_OFFSET_ADDR + 0x58)
#define REG_AFFINE_3D_MODE                      (VPC_AFFINE_OFFSET_ADDR + 0x50)
#define REG_AFFINE_3D_MODE_DEPTH                (VPC_AFFINE_OFFSET_ADDR + 0x54)

// region addr
#define REG_REGION_SIZE                         (VPC_REGION_OFFSET_ADDR + 0x0)
#define REG_REGION_CONCTRL                      (VPC_REGION_OFFSET_ADDR + 0x4)
#define REG_REGION_MOSAIC_CONCTRL               (VPC_REGION_OFFSET_ADDR + 0x10)
#define REG_REGION_MOSAIC_BLOCK                 (VPC_REGION_OFFSET_ADDR + 0x14)
#define REG_REGION_MOSAIC_HPOS                  (VPC_REGION_OFFSET_ADDR + 0x20)
#define REG_REGION_MOSAIC_VPOS                  (VPC_REGION_OFFSET_ADDR + 0x24)
#define REG_REGION_COVER_CONCTRL                (VPC_REGION_OFFSET_ADDR + 0x100)
#define REG_REGION_COVER_VALUE0                 (VPC_REGION_OFFSET_ADDR + 0x140)
#define REG_REGION_COVER_POS0_0                 (VPC_REGION_OFFSET_ADDR + 0x150)
#define REG_REGION_OSD_CONCTRL                  (VPC_REGION_OFFSET_ADDR + 0x400)
#define REG_REGION_OSD_ADDR_L                   (VPC_REGION_OFFSET_ADDR + 0x440)
#define REG_REGION_OSD_CLUT2_LAB_0              (VPC_REGION_OFFSET_ADDR + 0x700)
#define REG_REGION_OSD_CLUT4_LAB_0              (VPC_REGION_OFFSET_ADDR + 0x710)
#define REG_REGION_OSD_CSC_CTRL                 (VPC_REGION_OFFSET_ADDR + 0x800)
#define REG_REGION_OSD_CSC_0                    (VPC_REGION_OFFSET_ADDR + 0x810)

// rotate addr
#define REG_ROTATE_SRC_SIZE                     (VPC_ROTATE_OFFSET_ADDR + 0x00)
#define REG_ROTATE_MODE                         (VPC_ROTATE_OFFSET_ADDR + 0x04)
#define REG_ROTATE_SRC_ADDR_0_H                 (VPC_ROTATE_OFFSET_ADDR + 0x08)

// different chn vpc reg
extern const uint32_t REG_VPC_PIPELINE_OUT_SWAP_ADDR[3];
extern const uint32_t REG_VPC_OUT_444_TO_422_FILTER_ADDR[3];
extern const uint32_t REG_VPC_OUT_422_TO_420_FILTER_ADDR[3];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_ILEFT_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_IRIGHT_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_ITOP_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_IBOTTOM_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_OLEFT_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_ORIGHT_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_OTOP_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_OBOTTOM_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_MISC_CTRL_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_IN_WIDTH_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_IN_HEIGHT_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_OUT_WIDTH_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_OUT_HEIGHT_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_RESIZE_RND_CTRL0_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_POSTCROP1_1_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_POSTCROP1_2_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_POST_PADDING_VALUE_HOR_L_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_POST_PADDING_SIZE_0_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_POST_PADDING_SIZE_1_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_POST_PADDING_RESOLUTION_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_POST_PADDING_MODE_ADDR[2];
extern const uint32_t REG_VPC_PIPELINE_UVUP_FILTER_ADDR[3];
extern const uint32_t REG_VPC_PIPELINE_OUT_CSC_ENABLE_ADDR[3];
extern const uint32_t REG_VPC_PIPELINE_OUT_CSC_MODE_ADDR[3];
extern const uint32_t REG_VPC_PIPELINE_OUT_CSC_0_ADDR[3];
extern const uint32_t REG_VPC_PIPELINE_OUT_CSC_ALPHA_PADDING_ADDR[3];


extern uint32_t* VPC_VPRD_REG_MAP[11];
extern uint32_t* VPC_VPWR_REG_MAP[16];

#endif // #ifndef REG_VPC_MILAN_VPC_REG_H
